The present invention relates to semiconductor devices and more particularly to chip-scale flip-chip devices.
Because of their relatively small size chip-scale semiconductor devices have been used to increase the density of parts in an electronic circuit and/or reduce the size of an electronic circuit. Some chip-scale semiconductor device have a footprint which is the size of the die or nearly the size of the die. One way to obtain such a small footprint is to place all of the major electrodes on one of the major surfaces of the die. International Patent Application WO 01/59842 A1, entitled Vertical Conduction Flip-Chip Device with Bump Contacts on Single Surface, which is assigned to the assignee of the present invention, discloses a chip-scale flip-chip device which includes a die that has all its major electrodes disposed on one major surface thereof and is electrically mountable on a substrate via solder balls formed on its major electrodes. The device shown in WO 01/59841 A1 has a reduced footprint because its solder balls are positioned directly under the die when it is mounted thus making it possible to limit the size of the device to the size of the chip.
International Patent Application WO 01/75961, entitled Chip Scale Surface Mounted Device and Process of Manufacture, which is assigned to the assignee of the present application, shows a semiconductor device which has a semiconductor power MOSFET having two major electrodes on a first major surface thereof and another major electrode on a second major surface thereof. A passivation layer having a plurality of openings is disposed over the major electrodes on the first major surface of the MOSFET. The openings in the passivation layer are made through to a solderable top metal or a solderable surface can be formed over the exposed portions of the electrodes by nickel plating, gold flash or other series of metals so that solder may be received by the electrodes. In the device shown by WO 01/75961, the passivation layer acts as a plating resist, and a solder mask, designating and shaping the solder areas, as well as acting as a conventional passivation layer. The device shown in WO 01/75961 has a footprint that is close to the size of the chip because the connections to two of its three major electrodes are positioned directly under the power MOSFET.